Application-specific integrated circuits, or "ASICs," are circuits designed to satisfy the requirements of a particular electronic system. Designing an ASIC to implement a particular circuit function requires a number of steps. The first step is to create a design specification defining the function of the ASIC. The design specification sets forth the logic and timing parameters of the proposed circuit. Next, individual or teams of engineers design a circuit configuration that meets the design specification.
Circuit configurations are entered into an ASIC design system using either a hardware description language (HDL) and/or a schematic entry tool. HDLs represent circuits as lines of code, while schematic entry tools represent circuits using interconnected symbols that represent simple or complex logic functions. In either case, the logical components used to implement the circuit design are chosen from a library of ASIC cells that represent simple or complex logical operations. The resulting designs are then synthesized to produce a "netlist," a file that contains a description of all the components and interconnections in the circuit design.
The function and speed performance of ASIC cells are typically well characterized. Conventional design tools called logic simulators use custom test vectors and functional and timing information from the netlist to simulate the netlist to ensure that the design functions correctly. Next, a place-and-route tool determines the physical locations of the components in the netlist. Finally, the place-and-route tool defines the requisite connections between the various placed components.
FIG. 1A is a plan view of a gate array 100, an exemplary ASIC. Gate arrays begin as a nonspecific collection of logic gates. Late in the manufacturing process, metal layers are added to connect the gates. The manufacturer can configure the chip to perform any of myriad logic functions by changing the pattern of connections. This process is very popular because it saves both design and manufacturing time.
Gate array 100 includes a standard logic block 105 and a number of custom blocks 110, 120, and 130. Standard block 105 might be a conventional micro-controller, memory, or interface circuit that exists as part of an ASIC cell library. IC designers use standard blocks to save time. IC designers create custom blocks from collections of more basic cells to define custom logic functions.
Modern circuit designs are often far too complex to be designed by a single engineer--or even a single team of engineers--in a timely fashion. For this reason, complex circuit designs are typically broken down into functional blocks that are designed independently by design teams working concurrently. Separate sections of the design specification are allocated to different design groups. Each group is then tasked with designing a circuit block that meets the placement, logic, and timing requirements of one section, or "block," of the design specification.
Once the various block designs are complete, the blocks are compiled into a single netlist and are provided to another design team for placing and routing. FIG. 1B depicts the floor plan of FIG. 1A in which blocks 105, 110, 120, and 130 have been interconnected by a place-and-route tool.
FIG. 1B is illustrative; in practice, intrablock routing is vastly more complex. Not only are there a great many signal paths to define on a limited area, but the signal paths must often be manipulated by hand to solve timing problems and to improve circuit performance. Routing is therefore an iterative process of routing, simulating, troubleshooting, and rerouting. The processes of placing and routing an ASIC can add weeks or months to the implementation of a complex ASIC design.
ASICs are typically employed in products that have exceedingly short product lifetimes. Manufactures can affect the day at which a product is brought to market, but market forces typically dictate the end of product's lifetime. Time to market is therefore critical to profitability. There is therefore an ever-present need to speed the ASIC development process, and thereby reduce time to market.